Semiconductor Chokepoints: The Geopolitics of the Global Chip War

Context

The global semiconductor contest extends far beyond Taiwan's front-end foundries, hinging on acute geopolitical chokepoints across upstream critical mineral refining, photolithography equipment monopolies, and downstream advanced packaging architectures that dictate modern economic security and defence readiness. While leading-edge wafer fabrication remains concentrated, weaponised supply chains now target upstream feedstocks like gallium and specialised tooling machinery. In response, middle powers are deploying capital subsidies and forging plurilateral alliances to secure their industrial supply networks. India has entered this high-stakes landscape through the India Semiconductor Mission, pairing domestic fiscal incentives with multilateral critical mineral partnerships to build supply chain resilience.

Global semiconductor diplomacy has shifted rapidly from commercial trade negotiations to strategic national security interventions, led by bilateral technology pacts and retaliatory raw material export controls. As of January 2026, international chip competition is no longer defined solely by who manufactures the smallest microchip, but by who controls the indispensable nodes across the wider production network.

Geopolitical tensions between major trading blocs have accelerated unilateral trade measures and industrial policies. The United States has enforced sweeping export curbs on advanced computing chips and equipment, prompting counter-measures that target critical raw material supply chains. Consequently, nations are diversifying their strategic exposure across all stages of semiconductor production.

The Ministry of Electronics and Information Technology (MeitY) has positioned India within this shifting matrix by operationalising domestic fab investments and entering multilateral technology pacts. These cross-border partnerships aim to insulate vital industrial sectors from single-geography supply disruptions and state-directed export embargos.

The semiconductor supply chain represents one of the most intricate cross-border manufacturing networks in modern industrial history. According to a study by the Observer Research Foundation, the semiconductor value chain consists of five sequential stages:

1. Research and Electronic Design Automation (EDA): The upstream creation of chip architectures and specialized software tooling required to map billions of microscopic transistors on silicon.
2. Upstream Raw Mineral Extraction and Refining: The chemical isolation of foundational semiconductor elements, including high-purity polysilicon, compound semiconductor substrates, and strategic rare earths.
3. Semiconductor Manufacturing Equipment (SME) Fabrication: The production of specialized machinery, such as optical lithography scanners, chemical vapour deposition chambers, and precision metrology tools.
4. Front-End Wafer Fabrication (Foundries): The cleanroom-intensive physical printing and chemical etching of circuit patterns onto raw silicon wafers.
5. Back-End Assembly, Testing, Marking, and Packaging (ATMP/OSAT): The dicing of completed wafers into individual dies, followed by bonding, protective encapsulation, electrical testing, and integration into commercial modules.

Each stage exhibits extreme geographical concentration and massive capital barriers to entry. Front-end wafer fabrication has historically attracted the most public attention, yet a disruption at any preceding or succeeding stage halts global production entirely.

The true vulnerabilities of the global semiconductor network lie within highly concentrated supply bottlenecks outside pure foundry operations. These critical pressure points span specialized photolithography machinery, upstream chemical refining monopolies, and back-end integration facilities.

Photolithography and Tooling Monopolies

Front-end chip fabrication relies entirely on precision industrial tooling produced by a handful of specialized engineering firms. According to the Center for Strategic and International Studies (CSIS), Netherlands-based firm ASML holds a 100 percent global monopoly on commercial Extreme Ultraviolet (EUV) lithography systems. These EUV systems are irreplaceable for printing circuits at advanced sub-7nm process nodes.

Beyond photolithography, the broader equipment ecosystem is similarly consolidated. An analysis by the Observer Research Foundation shows that a tight oligopoly of five manufacturers—ASML, Applied Materials, Lam Research, Tokyo Electron, and KLA Corporation—controls over 70 percent of the global semiconductor manufacturing equipment market. This concentration enables equipment-producing nations to enforce extraterritorial export controls, effectively blocking rival foundries from acquiring critical maintenance tools and deposition systems.

Upstream Critical Mineral Vulnerabilities

The physical foundations of advanced microelectronics depend on a fragile supply of refined specialty minerals. Based on data from the USGS and the International Energy Agency (IEA), China produces over 80 percent of the world's refined gallium and roughly 60 percent of refined germanium. Gallium and germanium are indispensable compound semiconductor feedstocks utilized in high-frequency radio frequency (RF) chips, power electronics, telecommunications, and military radar photonics.

China's Ministry of Commerce leveraged this dependency by imposing strict export licensing controls on gallium and germanium items in August 2023. These restrictions were escalated in December 2024 under Notice No. 46 of 2024, which prohibited direct exports of these materials to the United States. Such restrictions demonstrate how upstream mineral dominance can be weaponised to counter downstream trade sanctions.

The Strategic Shift Toward Advanced Packaging

As physical scaling constraints decelerate classical Moore's Law, semiconductor engineering is shifting toward advanced back-end integration. A report by NITI Aayog notes that Advanced Packaging techniques—such as heterogeneous integration, 2.5D/3D stacking, and modular chiplets—now deliver crucial processing gains without demanding sub-3nm front-end fabrication nodes.

Outsourced Semiconductor Assembly and Test (OSAT) and ATMP facilities operate at significantly lower capital expenditure thresholds than front-end foundries. Building an advanced fabrication foundry requires an investment between $10 billion and $20 billion, whereas setting up an ATMP facility typically costs between $200 million and $3 billion. This lower capital barrier makes advanced packaging a viable, high-leverage entry point for developing nations seeking integration into the global semiconductor network.

Different nations dominate distinct segments of the semiconductor value chain, creating mutual interdependencies and strategic friction points. The following table contrasts the functional roles, technological strengths, and structural vulnerabilities of key players in the semiconductor ecosystem.

India has transitioned from conceptual policy discussions to deploying targeted capital subsidies aimed at anchoring domestic chip production. The Union Government launched the Programme for Development of Semiconductors and Display Manufacturing Ecosystem in India in December 2021 with an outlay of ₹76,000 crore.

The Union Government revised the financial assistance structure in September 2022 to provide uniform fiscal support. Under the modified guidelines, the Centre offers 50 percent fiscal support of the project cost on a pari-passu (equal footing) basis across all technology nodes for Silicon Fabs, Display Fabs, Compound Semiconductor units, and ATMP/OSAT facilities.

Upstream and Downstream Interventions

India's strategy tackles design capabilities, large-scale commercial manufacturing, and raw material access simultaneously:

• Design Linked Incentive (DLI) Scheme: Implemented by C-DAC under MeitY, this scheme offers financial reimbursements of up to 50 percent of eligible expenditure (capped at ₹15 crore per application) along with deployment incentives of 4 to 6 percent on net sales. As of January 2026, the DLI Scheme has supported 24 semiconductor chip design projects, resulting in 16 tape-outs and 6 operational ASIC chips across microprocessors, satellite communications, and IoT platforms.
• Commercial Fabrication Facilities: The Union Cabinet approved India's first commercial semiconductor fabrication facility in Dholera, Gujarat. The project is a ₹91,000 crore joint venture between Tata Electronics and Taiwan's Powerchip Semiconductor Manufacturing Corp (PSMC), designed for a capacity of 50,000 wafer starts per month across 28nm, 40nm, 55nm, and 90nm nodes.
• Advanced Packaging Footprint: Tata Semiconductor Assembly and Test Pvt Ltd (TSAT) is setting up an advanced ATMP unit in Morigaon, Assam, with an investment of ₹27,000 crore, focusing on flip-chip and integrated system-in-package (ISIP) technologies.
• Upstream Mineral Security: The Union Cabinet approved the National Critical Minerals Mission (NCMM) in January 2025 with an estimated outlay of ₹34,300 crore over seven years to secure domestic and overseas supply lines. This complements the Mines and Minerals (Development and Regulation) Amendment Act, 2023, which empowered the Central Government to exclusively auction mineral concessions for 24 critical and strategic minerals.

Semiconductor supply chain vulnerabilities have driven nations toward bilateral and minilateral technology alliances to de-risk their supply networks. India has leveraged strategic diplomacy to integrate domestic initiatives into trusted international coalitions.

India joined the US-led Minerals Security Partnership (MSP) as its 14th member in June 2023 to collaborate on critical mineral extraction, processing, and recycling. Bilaterally, under the India-US Initiative on Critical and Emerging Technology (iCET) established in January 2023, both nations signed a Semiconductor Supply Chain and Innovation Partnership Memorandum of Understanding to coordinate industrial incentives and workforce development.

Multilateral coordination extends to regional and European partners as well. The Quad Semiconductor Supply Chains Contingency Network maps critical supply bottlenecks and coordinates emergency responses to unexpected shortages across Australia, India, Japan, and the United States. Furthermore, the India-EU Trade and Technology Council (TTC) Working Group 2 established a Semiconductor Ecosystem Partnership in November 2023 to enhance research collaboration, workforce exchanges, and supply chain transparency.

Securing durable participation in the global semiconductor ecosystem requires India to balance aggressive domestic capacity creation with trusted international partnerships. A comprehensive strategy should focus on four structural priorities:

• Expanding the Design Linked Incentive Framework: Broaden the DLI scheme's financial limits to support indigenous Intellectual Property (IP) creation, fabless startups, and domestic RISC-V open-source microprocessor architectures.
• Accelerating Upstream Mineral Value Addition: Utilize the National Critical Minerals Mission to develop domestic refining and chemical processing facilities for gallium, germanium, and high-purity silicon, avoiding the trap of exporting unrefined raw ores.
• Capitalising on Legacy and Power Semiconductor Niches: Focus domestic fabrication on 28nm to 90nm legacy nodes and compound semiconductors (Silicon Carbide and Gallium Nitride), which serve high-volume domestic automotive, railway, and renewable power transmission markets.
• Institutionalising Plurilateral Supply Mechanisms: Operationalise the Quad Contingency Network and MSP agreements to establish regional semiconductor buffer reserves and emergency feedstock-sharing mechanisms during trade disputes.

• The semiconductor value chain comprises five distinct stages: R&D/EDA design, raw mineral refining, equipment manufacturing (SME), front-end fabrication, and back-end assembly/packaging (ATMP/OSAT).
• Critical industry chokepoints include ASML's 100 percent global monopoly on commercial EUV lithography machines and China's dominance over 80 percent of refined gallium and 60 percent of germanium production.
• Advanced packaging (ATMP/OSAT) has emerged as an economical entry point for emerging markets, requiring significantly lower capital investments ($200 million to $3 billion) than leading-edge foundries ($10 billion to $20 billion).
• India has operationalised a ₹76,000 crore incentive outlay offering 50 percent fiscal support across semiconductor segments, backing commercial projects including the Dholera fab and the Morigaon ATMP facility.
• The country is securing upstream supply chains through the ₹34,300 crore National Critical Minerals Mission and minilateral partnerships like the Minerals Security Partnership (MSP) and Quad technology networks.